1. Field of the Invention
The present invention generally relates to the design of integrated circuits. More specifically, the invention relates to reducing the failure rates of the nets of an integrated circuit due to soft errors without impacting the timing on critical paths of the circuit.
2. Background Art
With the continuing and increasing demand for electronic devices of all kinds, there is a concurrent need to improve the quality and to reduce the manufacturing time of these devices. In general, all electronic devices include at least one integrated circuit (“IC”) or “chip” which integrates millions of transistors and connections on one tiny substrate of semiconductor material. The miniaturization of integrated circuits, and the products which they control, continues to be of major significance in the marketplace and a driving force to the manufacturers of such products.
In designing integrated circuits, there are several key criteria which need to be optimized with respect to each other in order to create a design and an on-chip layout for an integrated circuit that provides the best overall results within certain cost and other design constraints. Such criteria include the size of the chip, power consumption of the chip and the speed of operation for the various functions accomplished within the chip. This kind of optimization analysis is normally done on a workstation or other computer system running various analysis and design programs which, in turn, operate to weigh the relative significance of the various design criteria for each specific application in which the designed integrated circuit will be implemented.
One of the most important of these design criteria is the time delay involved in a particular design for a digital signal to travel through a particular path or paths on the integrated circuit to get to certain key points or nodes of the circuit in the minimum time possible consistent with performance requirements. Ideally, the best design of an integrated circuit is the design that enables a signal to traverse a predetermined layout between certain key points in the smallest amount of time, wherein the layout or integrated circuit consumes minimal power and requires the smallest amount of semiconductor area to implement. In most cases, these criteria are mutually conflicting so that one cannot be improved without decreasing the efficacy of another at least to some extent.
For example, in the “sizing” of particular transistors for a proposed integrated circuit design, it is noted that although increasing the area of the transistors in the design will, in general, decrease the time delay in signal transmission, it will also increase the size and power of the chip, and therefore limit the applicability of the chip in certain product areas, as well as reduce the rofitability of the chip. Also, decreasing the size of a chip will, in general, decrease its power consumption, heat generation and chip signal interference.
Another important consideration is the selection of Qcrit for each net of the chip. Qcrit is the amount of charge that will cause a logic state reversal of the latch by causing a sufficiently large voltage disturbance. In the case of a DRAM cell, Qcrit is the amount of charge that will cause a logic state reversal by causing a sufficiently large leakage current to flow that will discharge the storage capacitor. Unfortunately, both miniaturization and lowered operating voltage (for example, the migration to 3.3 volt and beyond devices) of SRAM and DRAM cells with higher integration densities also reduce the value of Qcrit for stable operation of the memory cells. Accordingly, SRAMs and DRAMs have become increasingly vulnerable to errors of the type that are referred to as soft errors.
Soft errors in memory components used in digital components are spontaneous errors or changes in information stored in the memories that cannot be reproduced. Soft errors in electronic components are caused by a variety of electrical noise sources. For example, exposure to high energy particles, including particles produced by radioactivity or extraterrestrial cosmic rays, causes soft errors in electronic components.
The priority of each of the above design constraints and others, and the best possible solution for a particular application, will depend upon the application in which the integrated circuit is to be used. In most cases, the best result is obtained through a combination of trade-offs that is optimized with specific regard to, and consideration of, the specific application for the integrated circuit being designed.
In order to determine the level of optimization and evaluate the effectiveness of any particular design, certain analyses have been used in the industry. One such general evaluation technique is timing analysis. In this analysis, a circuit timing simulator evaluates a circuit (or macro, or chip) and produces a slack list. The slack list is a list of all nets in the system ordered by their timing difference from a predetermined nominal time. Those nets that are at or above their allocated timing are said to be “timing critical.” Those nets that are well within their allocated timing are not timing critical. In design iterations, those nets that meet their timing are left alone, and those nets that are over their allocated timing require redesign (and possible re-implementation at the logic level). Once all nets are on or under target, the design iteration process ends. While this procedure may effectively address circuit times, it is believed that, at least for many applications, these prior art procedures may not effectively address Qcrit.